{"id":57868,"date":"2026-05-26T09:47:09","date_gmt":"2026-05-26T07:47:09","guid":{"rendered":"https:\/\/www.nae.fr\/2026\/05\/26\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\/"},"modified":"2026-05-26T09:47:09","modified_gmt":"2026-05-26T07:47:09","slug":"fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks","status":"publish","type":"post","link":"https:\/\/www.nae.fr\/en\/2026\/05\/26\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\/","title":{"rendered":"Fault tolerance estimation in digital circuits with visualised generative networks"},"content":{"rendered":"<blockquote>\n<div class=\"summary\">\n<div class=\"crayon article-chapo-51727 article__chapo\">\n<p class=\"wp-block-paragraph\">We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals of a numerical experiment at the discriminator part of the Generative Adversarial Network (GAN) to calculate the deviation from ideal digital electronic signals, including various error modes, such as missing or interchanged logical devices. From the present analysis of a representation of the GAN in terms of complex variables, it is possible to evaluate the robustness in electronic designs by differentiating the impact of failure modes associated with different classical logical elements in the circuit.<\/p>\n\n<\/div>\n<\/div><\/blockquote>\nPour en savoir plus :\u00a0<a href=\"https:\/\/arxiv.org\/abs\/2605.15212\" target=\"_blank\" rel=\"noopener\">Fault tolerance estimation in digital circuits with visualised generative networks<\/a>","protected":false},"excerpt":{"rendered":"<p>We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":56493,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[34,16],"tags":[35,45,30],"class_list":["post-57868","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-innovation-et-technologique","category-rti","tag-actualites","tag-electrification-et-fiabilite-des-systemes-embarques","tag-fiabilite-des-systemes-et-des-composants"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Fault tolerance estimation in digital circuits with visualised generative networks - NAE<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.nae.fr\/en\/2026\/05\/26\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Fault tolerance estimation in digital circuits with visualised generative networks - NAE\" \/>\n<meta property=\"og:description\" content=\"We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals [&hellip;]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.nae.fr\/en\/2026\/05\/26\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\/\" \/>\n<meta property=\"og:site_name\" content=\"NAE\" \/>\n<meta property=\"article:published_time\" content=\"2026-05-26T07:47:09+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.nae.fr\/wp-content\/uploads\/2026\/06\/logo-cornell-university.png\" \/>\n\t<meta property=\"og:image:width\" content=\"225\" \/>\n\t<meta property=\"og:image:height\" content=\"225\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"adminwa\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"adminwa\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/\"},\"author\":{\"name\":\"adminwa\",\"@id\":\"https:\\\/\\\/www.nae.fr\\\/#\\\/schema\\\/person\\\/3d658e930f01449b7195ce4a78fcfc1e\"},\"headline\":\"Fault tolerance estimation in digital circuits with visualised generative networks\",\"datePublished\":\"2026-05-26T07:47:09+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/\"},\"wordCount\":154,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\\\/\\\/www.nae.fr\\\/#organization\"},\"image\":{\"@id\":\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.nae.fr\\\/wp-content\\\/uploads\\\/2026\\\/06\\\/logo-cornell-university.png\",\"keywords\":[\"Actualit\u00e9s\",\"Electrification et fiabilit\u00e9 des syst\u00e8mes embarqu\u00e9s\",\"Fiabilit\u00e9 des syst\u00e8mes et des composants\"],\"articleSection\":[\"Innovation et technologique\",\"RTI\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/\",\"url\":\"https:\\\/\\\/www.nae.fr\\\/2026\\\/05\\\/26\\\/fault-tolerance-estimation-in-digital-circuits-with-visualised-generative-networks\\\/\",\"name\":\"Fault tolerance estimation in digital circuits with visualised generative networks - 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