Gallium arsenide (GaAs) offers unique advantages in the fields of 5G communications and optoelectronics owing to its ultrahigh electron mobility and direct bandgap. However, its inherent low thermal conductivity leads to significant self-heating effects, which─along with the trend toward 3D heterogeneous integration and device miniaturization─adversely affect device performance and reliability. Here, 6-inch GaAs/SiC wafers are fabricated by the surface-activated bonding technique, exhibiting a dramatic improvement in heat dissipation efficiency compared to GaAs/Si counterparts, with a cooling ratio exceeding 66%. An intermixed thin amorphous layer (∼2.4 nm) at the interface is observed, and its influence on interfacial thermal conductance (ITC) is investigated by scanning transmission electron microscopy-electron energy loss spectroscopy (STEM-EELS) and molecular dynamics (MD) simulations. An optimal thickness of approximately 2 nm is identified to maximize the ITC of GaAs/SiC by enhancing the vibrational spectral overlap between bulk GaAs and SiC, while further increasing the thickness leads to strong phonon scattering. Our work demonstrates the feasibility of 6-inch wafer-scale GaAs/SiC integration and, beyond fabrication, provides mechanistic insights into interfacial thermal transport and offers practical guidance for engineering high-ITC interfaces toward high-power GaAs-based devices.
Direct Bonding of 6-inch GaAs/SiC Wafers for Enhanced Thermal Management in High-Power Devices
