This work presents a comprehensive study on the behaviour and operation of a vertical 1.2 kV 4H-SiC junctionless power FinFET. The increased bulk conduction in the channel of this topology may bring reductions in the channel resistance compared to trench MOSFETs, whose performance is limited by the high interface state density. For this purpose, finite element (FE) simulations are used to examine the operation of this device. It is hence demonstrated that the junctionless FinFET can attain a high average channel drift mobility well above 100 cm2/(Vs), leaving the resistance to be determined by the drift and substrate regions. This allows the FinFET to turn on and reach its steady state current using a much (> 3x) smaller gate overdrive than standard designs. On the other hand, however, the overly high field in the gate oxide, the lack of an efficient mechanism for hole extraction, and the low threshold voltage can cause significant reliability issues. Furthermore, it is shown that the high input capacitance of the FinFET can limit its switching speed to slower levels than in standard trench MOSFETs, which raises the need for further development of the original design proposed for vertical GaN devices. In this context, it is demonstrated that the addition of a p-shield below the trenches can alleviate the off-state reliability issues and increase the speed, while still maintaining a competitive Ron ∼ 2mΩ cm2 even without the use of n-JFET enhancement doping.